Many problems arise when it is necessary to interconnect a processing unit with one or more system busses which permit intercommunication to other memory modules, other processors and to other input/output systems. It is always necessary that there be taken into account means for allowing flexibility within the system, such as allowing partitioning, and also providing for system speed and also for proper data transfer integrity and correction, in addition to redundancy which might be required should one area fail.
Prior art systems such as U.S. Pat. No. 4,622,630 entitled "Data Processing System Having Unique Bus Control Protocol" involve a single common bus which is used for communication of address and data information among various system components but which single bus is time multiplexed in order to provide periods for address transfer and periods for data information transfer.
U.S. Pat. No. 4,982,321 entitled "Dual Bus System" provides an architecture where two system busses are used but for entirely different purposes. Thus one bus is operable for memory operations while another bus is operable for input/output operations but there is no redundancy or means by which each of the busses can be used for each of the other functions. Thus this system could not operate on a single bus since it at all times requires two busses for operations.
U.S. Pat. No. 4,535,448 entitled "Dual Bus Communication System" involves a dual set of busses used to provide coupling between data services and voice services of a particular AT&T communication system designated the CS300. One bus functions on a time division basis for communication between port circuits while the other bus functions as a packet-switch data processing bus for interfacing system peripherals with port circuitry. Again here the busses in this system are dissimilar and are not interchangeable to provide any redundancy.
U.S. Pat. No. 4,933,846 entitled "Network Communications Adapter With Dual Interleaved Memory Banks Servicing Multiple Processors" involves dissimilar busses such that one bus functions for transferring addresses and the other functions for the transfer of data. Then further this system operates for multiple computers hooked together in a network and does not function as a single computer hooked into dual common redundant busses.
The architecture of the presently disclosed system involves a single computer system operating independently but providing dual redundant system busses which have bus interface units which permit the processor and another element designated as the translation logic unit to communicate to either one of the two or dual system busses so that data communication and transfers may occur between the processor and other auxiliary resources such as a memory module, an input/output module, or another processor module if so desired. Each one of the two system busses involved is a duplicate of the other so that the system can operate on any one of the busses should the other one fail. Another feature of the present system is the flexibility of expansion so that a second central processing module system can be integrated for communication on the dual busses and permit partitioning into concurrently operating systems.
An ongoing problem in the operative functioning of these versatile computer and digital module intercooperating systems involves the time allocation and usage between various command cycles, control data cycles, message and data transfer cycles such that no single cycle will hang onto or monopolize the system busses causing access blockage and/or unnecessary delay, to the detriment of execution of other operational cycles.
The presently described programmable timing logic system serves to equitably allocate system bus time access to various resources which continually use the system busses, thus to minimize delays and access blockage of data transfer cycles.